VLSI implementation of residue number system based efficient digital signal processor architecture for wireless sensor nodes-Reference-Cited by-同舟云学术

VLSI implementation of residue number system based efficient digital signal processor architecture for wireless sensor nodes

Published:2019-03-18 Issue:4 Volume:11 Page:829-840
ISSN:2511-2104
Container-title:International Journal of Information Technology
language:en
Short-container-title:Int. j. inf. tecnol.

Author:

Ananthalakshmi A. V.,Rajagopalan P.

Funder

University Grants Commission

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Applied Mathematics,Artificial Intelligence,Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Information Systems

Link

http://link.springer.com/content/pdf/10.1007/s41870-019-00297-8.pdf

Reference18 articles.

1. Navi K, Molahosseini AS, Esmaeildous M (2011) How to teach residue number system to computer scientists and engineers. IEEE Trans Educ 54(1):156–163

2. Piestrak SJ (1995) A high-speed realization of residue to binary system converter. IEEE Trans Circ Syst II Analog Digit Signal Process 42(10):661–663

3. Dhurkadas A (1998) Comments on: a high-speed realization of a residue to binary number system converter. IEEE Trans Circ Syst II Analog Digit Signal Process 45(3):446–447

4. Bharadwaj M, Premkumar AB, Srikanthan T (1998) Breaking the 2n-bit carry propagation barrier in residue to binary conversion for the $$ \{ 2^{n } - 1, 2^{n} ,2^{n} + 1\} $$ { 2 n - 1 , 2 n , 2 n + 1 } -moduli set. IEEE Trans Circ Syst I Fundam Theory Appl 45(9):998–1002

5. Wang Y, Song X, Aboulhamid M, Shen H (2002) Adder based residue to binary number converters for {2n− 1, 2n, 2n+ 1}. IEEE Trans Signal Process 50(7):1772–1779

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