Author:
Leon German,Badia Jose M.,Belloch Jose A.,Lindoso Almudena,Entrena Luis
Abstract
AbstractGraphics processing units (GPUs) have become integral to embedded systems and supercomputing centres due to their large memory, cutting-edge technology and high performance per watt. However, their susceptibility to transient errors requires a comprehensive analysis of error sensitivity, as well as the development of error mitigation techniques and fault-tolerant algorithms. This study focuses on evaluating the soft-error sensitivity of two distinct versions of LU decomposition algorithms implemented on two very different GPUs—a low-power SoC embedded GPU and a high-performance massively parallel GPU. Through extensive fault injection campaigns on both GPUs, we examine the vulnerability of the algorithms, identify error causes, and determine critical code components requiring enhanced protection. The experiments reveal that most single bit flip fault injections in the instruction results lead to erroneous outcomes or unrecoverable errors. Notably, efficient GPU resource utilisation can increase the number of masked errors, thereby enhancing error resilience. Additionally, while different parts of the code exhibit similar error occurrence types and rates, the propagation of errors to elements within the result matrix differs significantly.
Funder
Ministerio de Ciencia e Innovación
Comunidad de Madrid
Universitat Jaume I
Publisher
Springer Science and Business Media LLC
Cited by
1 articles.
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1. Exploring the Behavior of Soft-Error Rate Reduction Algorithms in Digital Circuits;2024 International Conference on Optimization Computing and Wireless Communication (ICOCWC);2024-01-29