Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines-Reference-Cited by-同舟云学术

Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines

Published:2017-05-04 Issue:8 Volume:74 Page:3820-3840
ISSN:0920-8542
Container-title:The Journal of Supercomputing
language:en
Short-container-title:J Supercomput

Author:

Raji Mohsen,Ghavami Behnam

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Information Systems,Theoretical Computer Science,Software

Link

http://link.springer.com/article/10.1007/s11227-017-2056-0/fulltext.html

Reference33 articles.

1. Borkar S, Karnik T, Narendra S, Tschanz J, Keshavarzi A, De V (2003) Parameter Variations and Impact on Circuits and Micro-architecture. In: Proceedings of DAC, pp 338–342

2. Kiamehr S et al (2016) The Impact of Process Variation and Stochastic Aging in Nanoscale VLSI. In: 2016 IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, USA, pp CR-1-1–CR-1-6

3. Tang CK, Lin CY, Lu YC (2008) An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node. In: Proceedings of ISQED, pp 367 – 372

4. Beerel Peter A (2002) Asynchronous Circuits: An Increasingly Practical Design Solution. In: Proceedings of ISQED, pp 769–773

5. Nowick SM, Singh M (2015) Asynchronous design—part 1: overview and recent advances. IEEE Design Test 32(3):5–18

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