A neural network-based approach for the performance evaluation of branch prediction in instruction-level parallelism processors-Reference-Cited by-同舟云学术

A neural network-based approach for the performance evaluation of branch prediction in instruction-level parallelism processors

Published:2021-09-14 Issue: Volume: Page:
ISSN:0920-8542
Container-title:The Journal of Supercomputing
language:en
Short-container-title:J Supercomput

Author:

Nain Sweety^ORCID,Chaudhary Prachi

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Information Systems,Theoretical Computer Science,Software

Link

https://link.springer.com/content/pdf/10.1007/s11227-021-04045-3.pdf

Reference49 articles.

1. Sweety, Chaudhary P (2018) Branch prediction techniques used in pipeline processors: a review. Int J Pure Appl Math 119(15):2843–2851

2. Sweety, Chaudhary P (2020) Towards the improving branch instructions identification in high-performance processors issues, challenges and techniques. In: Recent Advances in Computer Science and Communications [Online]. Available: https://www.eurekaselect.com/node/191298/article/towards-the-improving-branch-instructions-identification-in-high-performance-processors-issues-challenges-and-techniques

3. Sweety, Chaudhary P (2020) Design and Fpga based implementation of 1-bit dynamic branch predictor for the parallelism processor. J Crit Rev 7(09):1156–1162. https://doi.org/10.31838/jcr.07.09.212

4. Sweety, Chaudhary P (2019) Implemented static branch prediction schemes for the parallelism processors. In: International Conference on Machine Learning, Big Data, Cloud and Parallel Computing (IEEE Xplore), pp 79–83. https://doi.org/10.1109/COMITCon.2019.8862216

5. Nain S, Chaudhary P (2021) Implementation and comparison of bi-modal dynamic branch prediction with static branch prediction schemes. Int J Inf Technol (Singap) 13(3):1145–1153. https://doi.org/10.1007/s41870-021-00631-z