DBU-PG: energy-efficient noc design using dual-buffering power gating
Author:
Funder
National Natural Science Foundation of China
Publisher
Springer Science and Business Media LLC
Link
https://link.springer.com/content/pdf/10.1007/s11227-024-06000-4.pdf
Reference29 articles.
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3. Yadav S, Laxmi V, Gaur MS (2020) Multiple-noc exploration and customization for energy efficient traffic distribution. In: 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), 200–201. https://doi.org/10.1109/VLSI-SOC46417.2020.9344101
4. Aligholipour R, Baharloo M, Farzaneh B, Abdollahi M, Khonsari A (2021) Tama: turn-aware mapping and architecture-a power-efficient network-on-chip approach. ACM Trans Embed Comput Syst 20(5). https://doi.org/10.1145/3462700
5. Farrokhbakht H, Kamali HM, Enright Jerger N (2019) Muffin: minimally-buffered zero-delay power-gating technique in on-chip routers. In: 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp 1–6. https://doi.org/10.1109/ISLPED.2019.8824806
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