Schedule Verification and Synthesis for Embedded Real-Time Components-Reference-Cited by-同舟云学术

Schedule Verification and Synthesis for Embedded Real-Time Components

Published:2007 Issue: Volume: Page:137-153
ISSN:
Container-title:Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems
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Author:

Bhaduri Purandar

Publisher

Springer Netherlands

Link

http://link.springer.com/content/pdf/10.1007/978-1-4020-6254-4_11.pdf

Reference14 articles.

1. Abdeddaïm, Yasmina, Kerbaa, Abdelkarim, and Maler, Oded (2003). Task graph scheduling using timed automata. In Parallel and Distributed Processing Symposium 2003. IEEE Computer Society.

2. Altisen, Karine, G ößler, Gregor, Pnueli, Amir, Sifakis, Joseph, Tripakis, Stavros, and Yovine, Sergio (1999). A framework for scheduler synthesis. In IEEE Real-Time Systems Symposium, pages 154-163.

3. Altisen Karine, Gößler Gregor, and Sifakis Joseph (2002). Scheduler modeling based on the controller synthesis paradigm. Real-Time Systems, 23(1-2):55-84.

4. Alur, Rajeev and Dill, David L. (1994). A theory of timed automata. Theoretical Computer Science, 126(2):183-235.

5. Caspi, Paul, Curic, Adrian, Maignan, Aude, Sofronis, Christos, Tripakis, Stavros, and Niebert, Peter (2003). From simulink to SCADE/Lustre to TTA: a layered approach for distributed embedded applications. ACM SIGPLAN Notices, 38(7):153-162.

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