1. M. J. Y. Williams and J. B. Angell. Enhancing Testability of Large Scale Integrated Circuits via Test Points and Additional Logic, IEEE Transaction on Computers, C-22, 46–60, 1973.
2. S. Funatsu, N. Wakatsuki, and T. Arima, Test Generation System in Japan, Proc. 12th Ann. Design Automation Conference, pp. 23–25, 1975.
3. E. B. Eichelberger and T. W. Williams A Logic Design Structure for LSI Testability, Proc. 14th Design Automation Conference, New Orleans, LA, pp. 462–468, June 1977.
4. T. W. Williams and N. C. Brown, Defect Level as a Function of Fault Coverage, IEEE Transactions on Computers, Vol. C-30, No. 12, Dec. 1981, 987–988.
5. T. W. Williams, R. H. Dennard, R. Kapur, M. R. Mercer, and W. Maley, Iddq Testing for High Performance CMOS - The Next Ten Years, Proc. 1996 European Design and Test Conference, Paris, France, pp. 578–583, March 1996.