Author:
Gupta Rajesh,Brewer Forrest
Cited by
11 articles.
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1. High-Level Synthesis Implementation of SAD for VVC Standard;2024 IEEE 7th International Conference on Advanced Technologies, Signal and Image Processing (ATSIP);2024-07-11
2. HLS and FPGA-Powered Streaming Video Encoder Accelerator for IoTs Edge Computing;Journal of Advances in Information Technology;2024
3. Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03
4. FPGA-Based Hardware/Software Codesign for Video Encoder on IoT Edge Platforms;Computational Science and Its Applications – ICCSA 2023 Workshops;2023
5. Big Data and HPC Acceleration with Vivado HLS;FPGAs for Software Programmers;2016