Digital twin based FPGA implementation of FIR filter for multi-bit soft computing error detection and correction for industrial applications
Author:
Publisher
Springer Science and Business Media LLC
Subject
Geometry and Topology,Theoretical Computer Science,Software
Link
https://link.springer.com/content/pdf/10.1007/s00500-022-07371-7.pdf
Reference35 articles.
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2. Afzaal U, Lee JA (2020) Trading the reliability of approximate TMR in FPGAs with the cost of mitigation. In: 23rd Euromicro conference on digital system design (DSD), Kranj, Slovenia, pp 660–663. https://doi.org/10.1109/DSD51259.2020.00107
3. Babic I, Miljkovic A, Cabarkapa M, Nikolic V, Đorđevic A, Ranđelovic M, Ranđelovic D (2021) Triple modular redundancy optimization for threshold determination in intrusion detection systems. Symmetry 13(4):557. https://doi.org/10.3390/sym13040557
4. Baumann R (2005) Soft errors in advanced computer systems. IEEE Des Test Comput 22(3):258–266
5. Benites LAC, Kastensmidt FL (2018) Automated design flow for applying triple modular redundancy (TMR) in complex digital circuits. In: IEEE 19th Latin-American test symposium (LATS), Sao Paulo, Brazil, pp 1–4. https://doi.org/10.1109/LATW.2018.8349668.
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