Hybrid on-chip soft computing model for performance evaluation of 6T SRAM cell using 45-nm technology
Author:
Publisher
Springer Science and Business Media LLC
Subject
Geometry and Topology,Theoretical Computer Science,Software
Link
http://link.springer.com/content/pdf/10.1007/s00500-019-04581-4.pdf
Reference33 articles.
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3. Biswas A, Chandrakasan AP (2018) CONV-SRAM: an energy-efficient SRAM with in-memory dot-product computation for low-power convolutional neural networks. IEEE J Solid-State Circuits 54(1):217–230
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5. Chen PY, Peng X, Yu S (2017) NeuroSim+: an integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures. In: 2017 IEEE international electron devices meeting (IEDM). IEEE, pp. 6–1
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