Exploiting dynamic transaction queue size in scalable memory systems

Author:

Marino Mario Donato,Weng Tien-Hsiung,Li Kuan-Ching

Publisher

Springer Science and Business Media LLC

Subject

Geometry and Topology,Theoretical Computer Science,Software

Reference48 articles.

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2. Binkert NL et al (2006) The M5 simulator: modeling networked systems. IEEE Micro 26(4):52–60

3. Bontempi G, Kruijtzer W (2004) The use of intelligent data analysis techniques for system-level design: a software estimation example. Soft Comput 8(7):477–490

4. Byun G et al (2011) An 8.4 Gb/s 2.5 pJ/b mobile memory I/O interface using bi-directional and simultaneous dual (base+RF)-band signaling. In: ISSCC, IEEE, pp 488, 490

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1. Research on global register allocation for code containing array‐unit dual‐usage register names;Concurrency and Computation: Practice and Experience;2022-12-05

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