Author:
Min Yinghua,Li Zhongcheng
Publisher
Springer Science and Business Media LLC
Subject
Computational Theory and Mathematics,Computer Science Applications,Hardware and Architecture,Theoretical Computer Science,Software
Reference16 articles.
1. McCluskey E J. Logic Design Principles. Prentice-Hall, 1986.
2. Joy D A, Ciesielski M J. Clock period minimization with wave pipelining.IEEE Trans. CAD, April 1993, 12(4): 461–472.
3. Gray C T, Liu W, Cavin R K. III, Timing constraints for wave-pipelined systems.IEEE Trans. CAD, August 1994, 13(8).
4. Yalcin H, Hayes J P. Hierarchical timing analysis using conditional delays. InProc. ICCAD, USA, Nov. 1995, pp. 371–377.
5. Kukimoto Yuji, Brayton R K. Hierarchical timing analysis under the XBDD model. InProc. Int. Workshop on Logic Synthesis, USA, May 1997.
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