Formal verification of pipelined processors
Author:
Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/BFb0054160
Reference7 articles.
1. S. Bose, and A. L. Fisher, “Verifying Pipelined Hardware Using Symbolic Logic Simulation,” International Conference on Computer Design (ICCD '89), 1989, pp. 217–221.
2. R. E. Bryant, “Symbolic Boolean Manipulation with Ordered Binary Decision Diagrams,” ACM Computing Surveys, Vol. 24, No. 3 (September, 1992), pp. 293–318.
3. J. R. Burch, and D. L. Dill, “Automated Verification of Pipelined Microprocessor Control,” Computer-Aided Verification (CAV'94), LNCS 818, Springer-Verlag, June, 1994, pp. 68–80.
4. C. A. R. Hoare, “Proof of Correctness of Data Representations,” Acta Informatica Vol. 1, 1972, pp. 271–281.
5. M. Kantrowitz, and L. M. Noack, “I'm Done Simulating; Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor,” 33rd Design Automation Conference (DAC '96), 1996, pp. 325–330.
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