1. Kim, S. K., Kim, J. Y., Jung, H. D., and Kim, J. H., “Simulation of Thermal Fatigue under Different Mold Compound and Chip Size for Wafer Level Embedded Sip,” Proc. of Korean Society of Machine Tool Engineers Conference, pp. 108–112, 2009.
2. Kim, T. H., Park, S. W., Hong, J. P., Gao, S., Jeon, J. Y., et al., “Study of Via-Hole Process for Wafer Level Package,” Proc. of KSPE Autumn Conference, pp. 359–360, 2008.
3. Park, S. M., Lee, H. J., and Park, S.-J., “Warpage Analysis of Large-Area Fan-Out Molding Process,” Proc. of the KSMTE, p. 108, 2012.
4. Tessier, T. G., Dhaenens, M., Clark, D., Karila, T., and Waris, T., “Laminate based Fan-Out Embedded Die Technologies: The Other Option,” Proc. of IWLPC Conference, 2010.
5. Fan, X., “Wafer Level Packaging (WLP): Fan-In, Fan-Out and Three-Dimensional Integration,” Proc. of 11th International Conference on Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems, pp. 1–7, 2010.