Low Power Optimized Array Multiplier with Reduced Area-Reference-Cited by-同舟云学术

Low Power Optimized Array Multiplier with Reduced Area

Published:2011 Issue: Volume: Page:224-232
ISSN:1865-0929
Container-title:High Performance Architecture and Grid Computing
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Author:

Devi Padma,Singh Gurinder pal,singh Balwinder

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-22577-2_30

Reference18 articles.

1. Marimuthu, C.N., Thangarj, P.: Low power high performance multiplier. ICGST International Journal on Programmable Devices, Circuits and Systems, PDCS 8(1), 31–38 (2008)

2. Krat, H., Al-Taie, A.Y.: Performance analysis of a 32-bit multiplier with a carry-look-ahead adder and a 32-bit multiplier with a ripple adder using VHDL. Journal of Computer Science 4, 305–308 (2008)

3. Lecture Notes in Computer Science;J.-G. Lee,2007

4. Amelifard, B., Fallah, F., Pedram, M.: Closing the gap between carry select adder and ripple carry adder: a new class of low-power high-performance adders. In: Proc. of IEEE International Symposium on Quality Electronic Design, ISQED (2005)

5. Zhijun, Huang: High-performance low-power left-to-right array multiplier design. IEEE Trans. Comput. 54(3), 272–283 (2005)

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