Using Binary Decision Diagram for Test Generation of Power Supply Noise in Digital Circuits
Author:
Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-31528-2_41.pdf
Reference11 articles.
1. Bohannon, E., Urban, C., Pude, M.: Passive and active reduction techniques for on-chip high-frequency digital power supply noise. IEEE Trans. on VLSI 18(1), 157–161 (2010)
2. Junxia, M., Mohammad, T.: Layout-aware critical path delay test under maximum power supply noise effects. IEEE Trans. on CAD 30(12), 1923–1934 (2011)
3. Tuuna, S., Tenhunen, H.: Skewing-based method for reduction of functional crosstalk and power supply noise caused by on-chip buses. IET Computers and Digital Techniques 6(2), 114–124 (2012)
4. Fiori, F.: On the use of high-impedance power supplies to reduce the substrate switching noise in system-on-chips. Microelectronics Reliability 52(1), 282–288 (2012)
5. Taparia, A., Banerjee, B., Viswanathan, T.R.: Power-supply noise reduction using active inductors in mixed-signal systems. IEEE Trans. on VLSI 19(11), 1960–1968 (2011)
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