A Delay and Distance Aware Code Mapping Technique for Coarse-Grained Reconfigurable Array Processors

Author:

Youn Jonghee,Cho Doosan

Publisher

Springer Berlin Heidelberg

Reference8 articles.

1. Kim, Y., Kiemb, M., Park, C., Jung, J., Choi, K.: Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization. In: Proceedings of DATE (2005)

2. Park, H., Fan, K., Kudlur, M., Mahlke, S.: Modulo Graph Embedding: Mapping Applications onto Coarse-Grained Reconfigurable Architectures. In: Proceedings of CASES (2006)

3. Mei, B., Vernalde, S., Verkest, D., De Man, H., Lauwereins, R.: DRESC: A Retargetable Compiler for Coarse-Grained Reconfigurable Architectures. In: Proceedings of CFP (2002)

4. Lee, C.G., Stoodley, M.G.: Simple vector microprocessors for multimedia applications. In: Proceedings of MICRO 31 (1998)

5. da Silva, M.V., Ferreira, R., Garcia, A., Cardoso, J.M.P.: Mesh mapping exploration for coarse grained reconfigurable array architectures. In: Proceedings of Reconfigurable Computing and FPGA’s (2006)

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