1. Aziz, A., Balarin, F., Brayton, R.-K., Sangiovanni-Vincentelli, A.-L.: Sequential synthesis using S1S. IEEE Trans. on CAD of Integrated Circuits and Systems 19(10), 1149–1162 (2000)
2. Anderson, T., Bergeron, J., Cerny, E., Hunter, A., Nightingale, A.: Systemverilog reference verification methodology: Introduction. EE Times, March 27 (2006)
3. Bloem, R., Cavada, R., Eisner, C., Pill, I., Roveri, M., Semprini, S.: Manual for property simulation and assurance tool (deliverable 1.2/4-5). Technical report, PROSYD Project (January 2004)
4. Boulé, M., Chenard, J.-S., Zilic, Z.: Adding debug enhancements to assertion checkers for hardware emulation and silicon debug. In: Proceedings of the 24th International Conference on Computer Design, ICCD 2006 (October 2006)
5. Bloem, R., Galler, S., Jobstman, B., Piterman, N., Pnueli, A., Weiglhofer, M.: Specify, compile, run: Hardware from PSL. Electronic Notes in Theoretical Computer Science (ENTCS) 190 (2007)