Single Thread Program Parallelism with Dataflow Abstracting Thread
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-13136-3_2.pdf
Reference20 articles.
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2. Kaul, M., Vemuri, R., Govindarajan, S., Ouaiss, I.: An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications. In: Proceedings of the 36th ACM/IEEE conference on Design automation (June 1999)
3. Bondhugula, U., Ramanujam, J., Sadayappan, P.: Automatic mapping of nested loops to FPGAS. In: Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming (March 2007)
4. Ottoni, G., Rangan, R., Stoler, A., August, D.I.: Automatic Thread Extraction with Decoupled Software Pipelining. In: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture (November 2005)
5. Bhowmik, Franklin, M.: A general compiler framework for speculative multithreading. In: Proceedings of the 14th ACM Symposium on Parallel Algorithms and Architectures, pp. 99–108 (2002)
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