An Efficient Finite-Element Method-Based Stress Simulator for Integrated Circuit Optimization Designs
Author:
Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-35398-7_30
Reference5 articles.
1. Moroz V, Smith L, Lin X, Pramanik D, Rollins G (2006) Stress—aware design methodology. In: Proceedings of the ISQED, vol 31(4). pp 807–812
2. Stutzke N, Cheek BJ, Kumar S (2003) Effects of circuit-level stress on inverter performance and MOSFET characteristics. In: Proceedings of the integrated reliability workshop final report, vol 10(6). pp 71–79
3. Miyamoto M, Ohta H, Kumagai Y, Ishibashi K, Tainaka Y (2009) Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics. IEEE Trans Electron Device 51(3):440–443
4. Moroz V, Eneman G, Verheyen P, Nouri F, Washington L, Smith L, Jurczak M, Pramanik D, Xu X (2005) The impact of layout on stress-enhanced transistor performance. In: Proceedings of the SISPAD, vol 28(15). pp 143–146
5. Luo Y, Nayak DK (2009) Enhancement of CMOS performance by process-induced stress. IEEE Trans Semicond Manuf 18(1):63–68
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