An Algorithm Based Concurrent Error Detection Scheme for AES
Author:
Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-17619-7_3
Reference22 articles.
1. Bertoni, G., Breveglieri, L., Koren, I., Maistri, P., Piuri, V.: On the propagation of faults and their detection in a hardware implementation of the advanced encryption standard. In: 13th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2002), p. 303 (2002)
2. Bertoni, G., Breveglieri, L., Koren, I., Maistri, P., Piuri, V.: A parity code based fault detection for an implementation of the advanced encryption standard. In: 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2002), p. 51 (2002)
3. Breveglieri, L., Koren, I., Maistri, P.: Incorporating error detection and online reconfiguration into a regular architecture for the advanced encryption standard. In: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2005), pp. 72–80 (2005)
4. Bertoni, G., Breveglieri, L., Koren, I., Maistri, P., Piuri, V.: Detecting and locating faults in VLSI implementations of the advanced encryption standard. In: 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), p. 105 (2003)
5. Bertoni, G., Breveglieri, L., Koren, I., Maistri, P., Piuri, V.: Error analysis and detection procedures for a hardware implementation of the advanced encryption standard. IEEE Transactions on Computers, 492–505 (April 2003)
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