Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit

Author:

Dasgupta Rituparna,Saha Dipankar,Samanta Jagannath,Chatterjee Sayan,Sarkar Chandan Kumar

Publisher

Springer Berlin Heidelberg

Reference9 articles.

1. Wang, Z.: Automatic V T Extractors Based on An nxn2 MOS Transistor Array and Their Application. IEEE J. Solid-State Circuits, 1277–1285 (1992)

2. Kang, S.M., Leblebici, Y.: CMOS Digital Integrated Circuits. Tata McGraw Hill Education Private Limited, New Delhi (2010)

3. Yu, C.G., Geiger, R.L.: An Accurate and Matching-free Threshold Voltage Extraction Scheme for MOS Transistors. In: Proc. IEEE International Symposium on Circuits and Systems, vol. 4, pp. 115–118 (1994)

4. Johnson, M.G.: An Input-Free V T Extractor Circuit Using a Two Transistor Differential Amplifier. IEEE J. Solid-State Circuits 28(6), 704–705 (1993)

5. Filanovsky, I.M.: An Input-Free V T Extractor Circuit Using a Series Connection of Three Transistors. Int. J. Electron. 82(5), 527–532 (1997)

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