Author:
Sruthi P. R.,Devi M. Nirmala
Publisher
Springer Berlin Heidelberg
Reference29 articles.
1. Hirech, M.: Test cost and test power conflicts: EDA perspective. In: Proceedings of the 28th IEEE VLSI Test Symposium (VTS 2010), Santa Cruz, Calif., USA, p. 126 (2010)
2. Hamzaoglu, I., Patel, J.H.: Reducing test application time for full scan embedded cores. In: Proc. Int. Symp. Fault-Tolerant Comput., pp. 260–267 (1999)
3. Jau-Shien, C., Chen-Shang, L.: Test set compaction for combinational circuits. In: Proceedings of Test Symposium, pp. 20–25 (1992)
4. Denq, L.-M., Hsing, Y.-T., Wu, C.-W.: Hybrid BIST scheme for multiple hetero-geneous embedded memories. IEEE Des. Test Comput. 26(2), 64–72 (2009)
5. Mehta, U.S., Dasgupta, K.S., Devashrayee, N.M.: Research Article: Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method. VLSI Design, Article ID 756561, 8 pages (2011)