Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip-Reference-Cited by-同舟云学术

Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip

Published:2012 Issue: Volume: Page:343-349
ISSN:0302-9743
Container-title:Progress in VLSI Design and Test
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Author:

Ghoshal Bibhas,Kundu Subhadip,Sengupta Indranil,Chattopadhyay Santanu

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-31494-0_39.pdf

Reference9 articles.

1. Marinissen, E.J., Prince, B., Keltel-Schulz, D., Zorian, Y.: Challenges in embedded memory design and test. In: Proceedings, Design, Automation and Test in Europe (DATE), vol. 2, pp. 722–727 (March 2005)

2. Bushnell, M.L., Agrawal, V.D.: Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. In: Frontiers in Electronic Testing. Kluwer Academic (2000)

3. Chien, T.-F., Chao, W.-C., Li, C.-M., Chang, Y.-W., Liao, K.-Y., Chang, M.-T., Tsai, M.-H., Tseng, C.-M.: Bist design optimization for large-scale embedded memory cores. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 197–200 (November 2009)

4. Huang, Y.-J., Li, J.-F.: A low-cost pipelined bist scheme for homogeneous rams in multicore chips. In: Proceedings, 17th Asian Test Symposium (ATS), pp. 357–362 (November 2008)

5. Denq, L.-M., Wu, C.-W.: A hybrid bist scheme for multiple heterogeneous embedded memories. In: Proceedings, 16th Asian Test Symposium (ATS), pp. 349–354 (October 2007)

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