Author:
Goudarzi Maziar,Ishihara Tohru,Noori Hamid
Publisher
Springer Berlin Heidelberg
Reference52 articles.
1. Moshnyaga, V.G., Inoue, K.: Low-Power Cache Design. In: Piguet, C. (ed.) Low-Power Electronics Design. CRC Press, Boca Raton (2005)
2. Roy, K., et al: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicron CMOS Circuits. Proc. IEEE (2003)
3. Taur, Y., Ning, T.H.: Fundamentals of Modern VLSI Devices. Cambridge University Press, Cambridge (1998)
4. Kao, J.T., Chandrakasan, A.P.: Dual-Threshold Voltage Techniques for Low-Power Digital Circuits. IEEE Journal of Solid State Circuits 35, 1009–1018 (2000)
5. Fallah, F., Pedram, M.: Circuit and System Level Power Management. In: Pedram, M., Rabaey, J. (eds.) Power Aware Design Methodologies, pp. 373–412. Kluwer Academic Pub., Dordrecht (2002)