1. Hu, Z., Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Jacobson, H., Bose, P.: Microarchitectural Techniques for Power Gating of Execution Units. In: International Symposium on Low Power Electronics and Design, pp. 32–37. ACM, New York (2004)
2. Popovich, M., Mezhiba, A., Friedman, E.: Power Distribution Networks with On-Chip Decoupling Capacitors. Springer, Heidelberg (2007)
3. Ho, H., Barth, J., Divakaruni, R., Ellis, W., Faltermeier, J., Anderson, B., Iyer, S., Kim, D., Mann, R., Parries, P.: Low-Cost Deep Trench Decoupling Capacitor Device and Process of Manufacture. U.S. Patent Number 7,193,262 (2007)
4. Knickerbocker, J., Andry, P., Dang, B., Horton, H., Interrante, M., Patel, C., Polastre, R., Sakuma, K., Sirdeshmukh, R., Sprogis, E., Sri-Jayantha, S., Stephens, A., Topol, A., Tsang, C., Webb, B., Wright, S.: Three-Dimension Silicon Integration. IBM Journal of Research and Development 52(6), 553–569 (2008)
5. Bergamaschi, R., Han, G., Buyuktosunoglu, A., Patel, H., Nair, I., Janssen, G., Dittman, G., Dhanwada, N., Hu, Z., Bose, P., Darringer, J.: Performance Modeling for Early Analysis of Multi-core System. In: The 5th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), pp. 209–214. ACM, New York (2007)