Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-11802-9_17
Reference8 articles.
1. Kuo, J.B.: Low-Voltage SOI CMOS Devices and Circuits. Wiley, New York (2004)
2. Usami, K., Kawabe, N., Koizuki, M., Seta, K., Furusawa, T.: Automated Selective Multi-Threshold Design for Ultra-Low Standby Applications. In: Low Power Electronics and Design Conf. Proc., pp. 202–206 (2002)
3. Kao, J., Narendra, S., Chandrakasan, A.: MTCNMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Pattern. In: Design Automation Conf. Proc., pp. 495–500 (1998)
4. Chung, B., Kuo, J.B.: Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application. Integration, the VLSI J., 9–16 (2008)
5. Assaderaghi, F., Sinitsky, D., Parke, S.A., Boker, J., Ko, P.K., Hu, C.: Dynamic Threshold- Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI. IEEE Trans. Elec. Dev., 414–422 (1997)
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