6 Efficient Technology Mapping Method for PAL-Based Devices

Author:

Kania Dariusz

Publisher

Springer Berlin Heidelberg

Reference26 articles.

1. Anderson, J.H., Brown, S.D.: Technology mapping for large complex PLDs. In: Proc. of Des. Autom. Conf., pp. 698–703 (1998)

2. Ashar, P., Devadas, S., Newton, A.R.: Sequential logic synthesis. Kluwer Academic Publisher, London (1992)

3. Bolton, M.: Digital systems design with programmable logic. Addison-Wesley Publishing Company, New York (1990)

4. Chen, S.L., Hwang, T.T., Liu, C.L.: A technology mapping algorithm for CPLD architectures. In: IEEE Int. Conf. on Field Program Technol., Hong Kong, pp. 204–210 (2002)

5. Ciesielski, M.J., Yang, S.: PLADE: A two-stage PLA decomposition. IEEE Trans. on Comput. Aided Des. 11, 943–954 (1992)

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