A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions-Reference-Cited by-同舟云学术

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A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

Published:2009 Issue: Volume: Page:205-219
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Regazzoni Francesco,Cevrero Alessandro,Standaert François-Xavier,Badel Stephane,Kluter Theo,Brisk Philip,Leblebici Yusuf,Ienne Paolo

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-04138-9_15

Reference29 articles.

1. Alioto, M., Palumbo, G.: Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits. Springer, Dordrecht (2005)

2. Allam, M.W., Elmasry, M.I.: Dynamic current mode logic (DyCML): A new low-power high-performance logic style. IEEE Journal of Solid-State Circuits 36(3), 550–558 (2001)

3. Badel, S., Guleyupoglu, E., Inac, O., Martinez, A.P., Vietti, P., Gürkaynak, F.K., Leblebici, Y.: A generic standard cell design methodology for differential circuit styles. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Munich, March 2008, pp. 843–848 (2008)

4. Bartolini, S., Branovic, I., Giorgi, R., Martinelli, E.: A performance evaluation of ARM ISA extension for elliptic curve cryptography over binary finite fields. In: Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing, Foz do Igua cu, Brazil, October 2004, pp. 238–245 (2004)

5. Lecture Notes in Computer Science;A. Bogdanov,2007

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