Improved-XY: A High Performance Wormhole-Switched Routing Algorithm for Irregular 2-D Mesh NoC
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-22185-9_9
Reference17 articles.
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3. Pande, P., Grecu, C., Jones, M., et al.: Performance Evaluation and Design Trade-Offs for Network-on- Chip Interconnect Architectures. IEEE Trans. Computers 54(8), 1025–1040 (2005)
4. Palesi, M., Holsmark, R., Kumar, S., et al.: Kumar, Sh., et al.: Application Specific Routing Algorithms for Networks on Chip. IEEE Trans. on Parallel and Distributed Systems 20(3), 316–330 (2009)
5. Guerrier, P., Greiner, A.: A generic architecture for on-chip packet-switched interconnections. In: Proceedings Design Automation and Test in Europe Conference and Exhibition, Paris, France, March 2000, pp. 250–256 (2000)
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