Author:
Núñez Juan,Avedillo María J.,Quintana José M.
Publisher
Springer Berlin Heidelberg
Reference4 articles.
1. Núñez, J., Avedillo, M.J., Quintana, J.H.: Efficient realization of MOS-NDR threshold logic gates. IET Electronics Letters 45(23), 1158–1160 (2009)
2. Gan, K.-J., et al.: Four-valued memory circuit using three-peak MOS-NDR devices and circuits. IET Electronics Letters 42(9), 514–515 (2006)
3. Lin, C.-H., et al.: InP-based high speed digital logic gates using an RTD/HBT heterostructure. In: Proceedings of the Eleventh International Conference on Indium Phosphide and Related Materials, pp. 419–422 (1999)
4. Wuu, T.-Y., Vrudhla, S.B.K.: A design of a fast and area efficient multi-input Muller C-element. IEEE Transaction on Very Large Scale Integration (VLSI) Systems 1(2), 215–219 (1993)