1. Pelgrom, M.J.M., Duinmaijer, A.C.J., Welbers, A.P.G.: Matching Properties of MOS Transistors. IEEE J. Solid-State Circuits 24(5), 1433–1439 (1989)
2. Flynn, M.P., Donovan, C., Sattler, L.: Digital Calibration Incorporating Redundancy of Flash ADCs. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 50(5), 205–213 (2003)
3. Li, X., Taylor, B., Chien, Y., Pileggi, L.T.: Adaptive Post-Silicon Tuning for Analog Circuits: Concept, Analysis and Optimization. In: IEEE/ACM Int. Conf. on Computer-Aided Design Dig. Tech. Papers, pp. 450–457 (November 2007)
4. Agarwal, K., Nassif, S.: Characterizing process variation in nanometer CMOS. In: Proc. ACM/IEEE Design Automation Conf., pp. 396–399 (June 2007)
5. Scott, G., et al.: NMOS drive current reduction caused by transistor layout and trench isolation induced stress. In: IEEE Int. Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 827–830 (December 1999)