Formal Verification of DEV&DESS Formalism Using Symbolic Model Checker HyTech-Reference-Cited by-同舟云学术

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Formal Verification of DEV&DESS Formalism Using Symbolic Model Checker HyTech

Published:2011 Issue: Volume: Page:112-121
ISSN:1865-0929
Container-title:Communications in Computer and Information Science
language:
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Author:

Choi Han,Cha Sungdeok,Jo Jae Yeon,Yoo Junbeom,Lee Hae Young,Kim Won-Tae

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-26010-0_13

Reference22 articles.

1. Alur, R., Courcoubetis, C., Halbwachs, N., Henzinger, T.A., Ho, P.H., Nicollin, X., Olivero, A., Sifakis, J., Yovine, S.: The algorithmic analysis of hybrid systems. Theoretical Computer Science 138(1), 3–34 (1995)

2. Alur, R., Dang, T., Esposito, J., Hur, Y., Ivančić, F., Vijay Kumar, I.L., Mishra, P., Pappas, G.J., Sokolsky, O.: Hierarchical modeling and analysis of embedded systems. Proceedings of the IEEE 91(1), 11–28 (2003)

3. Alur, R., Dill, D.L.: A theory of timed automata. Theoretical Computer Science 126 (1994)

4. Alur, R., Henzinger, T.A., Ho, P.H.: Automatic symbolic verification of embedded systems. IEEE Transactions on Software Engineering 22(3), 181–201 (1996)

5. Lecture Notes in Computer Science;P.J. Antsaklis,1995

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Translation from ECML to Linear Hybrid Automata;Lecture Notes in Electrical Engineering;2012

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