Author:
Negrini Roberto,Stefanelli Renato
Publisher
Springer Berlin Heidelberg
Reference18 articles.
1. C.H. Stapper, “Modeling of Integrated Circuits Defect Sensitivities”, IBM Journal of Research and Development, vol. 27, n. 6, pp. 549–557 (nov. 1983 )
2. W.R. Moore, “A Review of Fault- Tolerant Techniques for the Enhancement of Integrated Circuit Yield”, Proceedings of the IEEE, Special issue on Fault-Tolerance for VLSI (may 1986 )
3. R. Negrini, M.G. Sami, N. Scarabottolo, “Policies for System-Level Diagnosis in a Nonhierarchical Distributed System”, IEEE Trans, Reliab. (Oct. 1984)
4. D.P. Siewiorek, R.S. Swarz, The Theory and Practice of Reliable System Design, Digital Press, Bedford (1982)
5. R.M. Mangir, A. Avizienis, “Fault-tolerant design for VLSI: effect of interconnection requirements on yield improvement of VLSI design”, IEEE Trans. Comp., vol. C31, n. 7, pp. 609–615 (July 1982)
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献