1. Palesi, M., Holsmark, R., Kumar, S., Catania, V.: Application Specific Routing Algorithms for Networks on Chip. IEEE Trans. Parallel and Distributed Systems. 20, 316–330 (2009)
2. Dally, W.J., Towles, B.: Route Packets, Not Wires: On-Chip Interconnection Networks. In: Design Automation Conf., pp. 684–689 (2001)
3. Benini, L., De Micheli, G.: Networks on Chips: A New SoC Paradigm. Computer 35, 70–78 (2002)
4. Millberg, M., Nilsson, E., Thid, R., Kumar, S., Jantsch, A.: The Nostrum backbone - a communication protocol stack for networks on chip. In: VLSI Design Conference, pp. 693–696 (2004)
5. Rijpkema, E., Goossens, K., Wielage, P.: A router architecture for networks on silicon. In: 2nd Workshop on Embedded Systems (2001)