Complexities of Performance Prediction for Bandwidth-Limited Loop Kernels on Multi-Core Architectures-Reference-Cited by-同舟云学术

Complexities of Performance Prediction for Bandwidth-Limited Loop Kernels on Multi-Core Architectures

Published:2010 Issue: Volume: Page:3-12
ISSN:
Container-title:High Performance Computing in Science and Engineering, Garching/Munich 2009
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Author:

Treibig Jan,Hager Georg,Wellein Gerhard

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-13872-0_1.pdf

Reference4 articles.

1. W. Schönauer: Scientific Supercomputing: Architecture and Use of Shared and Distributed Memory Parallel Computers. Self-edition, Karlsruhe (2000).

2. K. Datta, M. Murphy, V. Volkov, S. Williams, J. Carter, L. Oliker, D. Patterson, J. Shalf, K. Yelick: Stencil Computation Optimization and Auto-tuning on State-of-the-Art Multicore Architectures. In: ACM/IEEE (Ed.): Proceedings of the ACM/IEEE SC 2008 Conference (Supercomputing Conference ’08, Austin, TX, Nov 15–21, 2008).

3. Intel Corporation: Intel 64 and IA-32 Architectures Optimization Reference Manual. (2008) Document Number: 248966–17.

4. W. Jalby, C. Lemuet and X. Le Pasteur: WBTK: a New Set of Microbenchmarks to Explore Memory System Performance for Scientific Computing. International Journal of High Performance Computing Applications, Vol. 18, 211–224 (2004).

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