Author:
Bechara Charly,Ventroux Nicolas,Etiemble Daniel
Publisher
Springer Berlin Heidelberg
Reference14 articles.
1. Duranton, M., Yehia, S., De Sutter, B., De Bosschere, K., Cohen, A., Falsafi, B., Gaydadjiev, G., Katevenis, M., Maebe, J., Munk, H., Navarro, N., Ramirez, A., Temam, O., Valero, M.: The HiPEAC Vision. HiPEAC Network of Excellence (2010)
2. Lacassagne, L., Zavidovique, B.: Light speed labeling: efficient connected component labeling on RISC architectures. Journal of Real-Time Image Processing, 1–19 (2009), doi:10.1007/s11554-009-0134-0
3. Wall, D.W.: Limits of instruction-level parallelism. In: Int’l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Santa Clara, USA (April 1991)
4. Bertogna, M., Cirinei, M., Lipari, G.: Schedulability Analysis of Global Scheduling Algorithms on Multiprocessor Platforms. IEEE Transactions on Parallel and Distributed Systems 20(4), 553–566 (2008)
5. Ventroux, N., David, R.: The SCMP architecture: A Heterogeneous Multiprocessor System-on-Chip for Embedded Applications. Eurasip (2009)