A Dual-Threshold CMOS Technique of P-Type CAL Circuits for Leakage Reduction
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-19712-3_28.pdf
Reference12 articles.
1. Roy, K., Mukhopadhyay, S., et al.: Leakage Current Mechanisms and Leakage Reduction Technique in Deep-submicrometer CMOS Circuits. Proceeding of IEEE 91(2), 305–327 (2003)
2. Kim, N.S., Austin, T., et al.: Leakage Current: Moore’s Law Meets Static Power. Computer 36(12), 68–75 (2003)
3. Hamzaoglu, F., Stan, M.R.: Circuit-Level Techniques to Control Gate Leakage for Sub-100 nm CMOS. In: Proc. Int. Symp. Low Power Electronics and Design, pp. 60–63 (2002)
4. Fallah, F., Pedram, M.: Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits. IEICE Trans. on Electronics E88–C(4), 509–519 (2005)
5. Wei, L., Chen, Z., Johnson, M., Roy, K.: Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. In: Proc. Annual ACM IEEE Design Automation Conference, pp. 489–492 (1998)
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