ERA: An Efficient Routing Algorithm for Power, Throughput and Latency in Network-on-Chips

Author:

Sharma Varsha,Agarwal Rekha,Gaur Manoj S.,Laxmi Vijay,V. Vineetha

Publisher

Springer Berlin Heidelberg

Reference18 articles.

1. Dally, W.J., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Annual Design Automation Conference, Las Vegas, Nevada, United States, pp. 684–689. ACM, New York (2001)

2. Hu, J., Marculescu, R.: Dyad smart routing for network-on-chip. In: 41st Design Automation Conference (2004)

3. Chiu, G.-M.: The odd-even turn model for adaptive routing. IEEE Transactions on Parallel and Distributed Systems, 729–738 (2000)

4. Glass, C., Ni, L.: The turn model for adaptive routing. In: 19th Annual International Symposium, Computer Architecture, pp. 278–287 (1992)

5. Jain, L., Al-Hashimi, B., Gaur, M.S., Laxmi, V., Narayanan, A.: Nirgam: A simulator for noc interconnect routing and application modelling. In: Design Automation and Test in Europe (DATE), Nice, France (2007)

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