An Efficient Lightweight Shared Cache Design for Chip Multiprocessors
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-03644-6_3
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4. Vangal, S., Howard, J., Ruhl, G., et al.: An 80-tile 1.28tflops network-on-chip in 65nm cmos. In: IEEE Int’l. Solid-State Circuits Conference (ISSCC) (February 2007)
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