Author:
Mukherjee Rajdeep,Ghosh Priyankar,Dasgupta Pallab,Pal Ajit
Publisher
Springer Berlin Heidelberg
Reference20 articles.
1. Hwang, C.T., Lee, J.H., Hsu, Y.C.: A formal approach to the scheduling problem in high level synthesis. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 10(4), 464–475 (1991)
2. Paulin, P.G., Knight, J.P.: Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 8(6), 661–679 (1989)
3. De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill Higher Education (1994)
4. Katkoori, S., Vemuri, R.: Scheduling for low power under resource and latency constraints. In: Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 2, pp. 53–56 (2000)
5. Putic, Di Liang, M., Calhoun, B., Lach, J.: Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design. In: Proceedings of the IEEE International Conference on Computer Design, pp. 491–497 (October 2009)