Energy Efficient All-Digital Phase Locked Loop Architecture Design on High Resolution Fast Clocking Time to Digital Converter (TDC) Using Model Prescient Control (MPC) Technique

Author:

Sathish Kumar T. M.,Periasamy P. S.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Reference22 articles.

1. Yoo, J., & Rieh, J. S. (2017). CMOS 120 GHz phase-locked loops based on two different VCO topologies. Journal of Electromagnetic Engineering and Science, 17(2), 98–104. https://doi.org/10.5515/JKIEES.2017.17.2.98 .

2. Jang, T., Jeong, S., Jeon, D., Choo, K. D., Sylvester, D., & Blaauw, D. (2014). A noise reconfigurable all-digital phase-locked loop using a switched Capacitor-Based Frequency-Locked Loop and a Noise Detector. Circuits, (99), 1–20.

3. Jang, S., Kim, S., Chu, S.-H., Jeong, G.-S., Kim, Y., & Jeong, D.-K. (2015). An optimum loop gain tracking all-digital PLL using autocorrelation of bang–bang phase-frequency detection. IEEE Transactions on Circuits and Systems II: Express Briefs, 62(9), 20–39.

4. Cheng, K.-H., Hu, C.-C., Liu, J.-C., & Huang, H.-Y. (2010). A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. In Design and diagnostics of electronic circuits and systems (DDECS), 2010 (Vol. 45, pp. 20–37).

5. Hussein, A. I., Vasadi, S., & Paramesh, J. (2015). A 450 fs 65-nm CMOS millimeter-wave time-to-digital converter using statistical element selection for all-digital PLLs. IEEE Journal of Solid-State Circuits,(99), 20–42.

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