High Reliability Soft Error Hardened Latch Design for Nanoscale CMOS Technology using PVT Variation
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Computer Science Applications
Link
https://link.springer.com/content/pdf/10.1007/s11277-022-10033-4.pdf
Reference21 articles.
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3. Ming, Z., Yi, X. L., Chang, L., & Wei, Z. J. (2011). Reliability of memories protected by multibit error correction codes against MBUs. IEEE Transactions on Nuclear Science, 58(1), 289–295
4. Xuan, S. X., Li, N., & Tong, J. (2013). SEU hardened flip-flop based on dynamic logic. IEEE Transactions on Nuclear Science, 60(5), 3932–3936
5. Montesinos, P., Liu, W., & Torrellas, J. (2007). Using register lifetime predictions to protect register files against soft errors. In Proceedings of37th Annual IEEE/FIP International Conference on Dependable Systems and Networks (DSN’07) (pp. 286-296). Edinburgh, UK
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