Design of Energy Efficient Multiplier with Approximate Computing on Scalable Compressor for Error-Resilient Image Contrast Enhancement

Author:

Savio M. Maria Dominic,Deepa T.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Reference33 articles.

1. Kuo, S. M., Lee, B. H., & Tian, W. (2013). Real-time digital signal processing: Fundamentals, implementations and applications. Wiley.

2. Dandapat, A., Ghosal, S., Sarkar, P., & Mukhopadhyay, D. (2010). A 1.2-ns 16 × 16-bit binary multiplier using high speed compressors. International Journal of Electrical and Electronics Engineering, 4(3), 234–239.

3. Parhi, K. K. (1999). VLSI digital signal processing systems: Design and implementation (1st ed.). Wiley.

4. Parhami, B. (2010). Computer arithmetic. Oxford University Press.

5. Mittal, S. (2016). A survey of techniques for approximate computing. ACM Computing Surveys (CSUR), 48(4), 1–33.

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