FM Receiver Design Using Programmable PLL-Reference-Cited by-同舟云学术

FM Receiver Design Using Programmable PLL

Published:2017-05-29 Issue:1 Volume:97 Page:773-787
ISSN:0929-6212
Container-title:Wireless Personal Communications
language:en
Short-container-title:Wireless Pers Commun

Author:

Kumar Adesh,Verma Gaurav,Gupta Mukul Kumar

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

http://link.springer.com/article/10.1007/s11277-017-4536-1/fulltext.html

Reference20 articles.

1. Rylyakov, A. V., Tierno, J. A., Plouchart, J.-O., Turker, D. Z., Ainspan, H. A., & Friedman, D. (2008). A modular all-digital PLL architecture enabling both 1-to-2 GHz operation in 65 nm CMOS. In IEEE International Solid-State Circuits Conference, IEEE Xplorer, pp. 516–632.

2. Fahim, A. M. (2005). Clock generators for SOC processors, Ch–2 (pp. 3–24). Dordrecht: Kluwer Academic Publisher.

3. Huang, C.-H., Chen, Y.-C., & Jong, G.-J. (2011). The FPGA implementation of amplitude-locked loop system for co-channel communication chip design. In CSEE, pp. 458–461. Springer, Berlin.

4. Wang, C.-C., Sung, G.-N., Huang, J.-M., & Lin, L.-P. (2007). An 80 MHz PLL with 72.7 ps peak-to-peak jitter. Microelectronics Journal, 38, 716–721.

5. Stephens, D. R. (2002). Phase-locked loops for wireless communication, digital, analog and optical implementations, Ch-1 (pp. 11–58). Dordrecht: Kluwer Academic Publisher.

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