Accomplishment of Reversible Logic Gates in WSN Environment by Patternization

Author:

Kirankumar M.ORCID,Santhi M.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Reference35 articles.

1. Parvin, S., & Altun, M. (2019) Perfect concurrent fault detection in CMOS Logic circuits using parity preservative reversible gates. IEEE Access, 7, 163939–163947

2. Khatter P., Pandey N., & Gupta, K. (2018) An arithmetic and logical unit using reversible gates. 2018 international conference on computing, power and communication technologies (GUCON) Galgotias University, Greater Noida, UP, India

3. Naik SM., Bhat MR., Ramesh N., Ashwini B, An optimized reversible signed comparator. Proceeding of second international conference on circuits, controls and communications

4. M. Aditya, Y.B. Nithin Kumar, M.H. Vasantha, “Reversible full/half adder with optimum power dissipation

5. Anamika, Rockey Bhardwaj Reversible logic gates and its performances IEEE Xplore Compliant - Part Number: CFP18J06-ART, ISBN:978–1–5386–0807–4

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