Design techniques for high speed serial data transmitters in CMOS process
Author:
Publisher
Springer Science and Business Media LLC
Subject
General Engineering,Applied Mathematics,Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/BF01232920.pdf
Reference6 articles.
1. Kang, J.; Liu, W.; Cavin, R. K.: A Monolithic 625 Mbps Data Recovery Circuit in 1.2 ?m CMOS. Proc. of Custom Integrated Circuits Conference (1994) 27.3.1?27.3.4
2. Banu, M.; Dunlop, A.: A 660 Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst Mode Transmission. Proc. of International Solid State Circuits Conference (1993) 102?103
3. Yoo, C.;Kim, M.-K.;Kim, W.: A Static Power Saving TTL-to-CMOS Input Buffer. IEEE J. Solid State Circuits Vol. 30 No. 5 (1995) 616?620
4. Steyaert, M. S. J.;et al.: ECL-CMOS and CMOS-ECLInterface in 1.2 ?m CMOS for 150 MHz Digital ECL Data Transmission Systems. IEEE J. Solid State Circuits. Vol. 26 No. 1 (1991) 18?23
5. Wolaver, D. H.: Phase-Locked Loop Circuit Design. Prentice-Hall 1991
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