1. Kobayashi, T.; Matsue, T.; Shiba, H.: Flip-Flop circuit with FLT capability. Proc. IECEO Conf. (1968) 962 (in Japanese)
2. Williams, M. J. Y.;Angell, J. B.: Enhancing testability of large-scale integrated circuits via test points and additional logic. IEEE Trans. Comput. C-22, January (1973) 46?60
3. Eichelberger, E. B.; Williams, T. W.: A logic design structure for LSI testability. Proc. 14th ACM/IEEE Design Automation Conf., June 1977, 462?464
4. Beenker, F. P. M.: Systematic and structured methods for digital board testing. Proc. IEEE International Test Conf., Philadelphia, 1985, 380?385
5. IEEE Standard 1149.1-1990, IEEE standard test access port and boundary-scan architecture. IEEE Standards Board, 345 East 47th Street, New York, NY 10017, May 1990