A new classification approach for neural networks hardware: from standards chips to embedded systems on chip

Author:

Izeboudjen N.,Larbes C.,Farah A.

Publisher

Springer Science and Business Media LLC

Subject

Artificial Intelligence,Linguistics and Language,Language and Linguistics

Reference136 articles.

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3. AN221E04 Datasheet (2010) Dynamically reconfigurable FPAA with Enhanced I/O, DS030100-U006b. Available in the internet at: http://www.anadigm.com (accessed November 2011)

4. Anderson D, McNeill G (1992) Artificial neural networks technology. DACS State-of-the-Art Report, Contract Number F30602-89-C-0082

5. Ayala JL et al. (2002) Design of a pipelined hardware architecture for real-time neural network computations. In: Proceedings of the 45th midwest symposium on circuits and systems MWSCAS’02 Tulsa, Okla, USA, vol 1, pp 419–422

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