Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture-Reference-Cited by-同舟云学术

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Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture

Published:2005 Issue: Volume: Page:213-222
ISSN:0302-9743
Container-title:High Performance Computing and Communications
language:
Short-container-title:

Author:

Villa Francisco J.,Acacio Manuel E.,García José M.

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/11557654_27

Reference20 articles.

1. Barroso, L.A., Gharachorloo, K., McNamara, R., Nowatzyk, A., Qadeer, S., Sano, B., Smith, S., Stets, R., Verghese, B.: Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing. In: Proc. of 27th Int’l Symp. on Computer Architecture, pp. 282–293 (2000)

2. Hammond, L., Hubbert, B.A., Siu, M., Prabhu, M.K., Chen, M., Olukotun, K.: The Stanford Hydra CMP. IEEE Micro 20, 71–84 (2000)

3. Kalla, R., Sinharoy, B., Tendler, J.M.: IBM Power5 Chip: A Dual-Core Multithreaded Processor. IEEE Micro 24, 40–47 (2004)

4. Krewell, K.: UltraSPARC IV Mirrors Predecessor. Micro. Report, pp. 1-3 (2003)

5. Hughes, C.J., Pai, V.S.P., Ranganathan, P., Adve, S.V.: RSIM: Simulating Shared-Memory Multiprocessors with ILP Proccesors. IEEE Computer 35, 68–76 (2002)

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. L2-Cache Hierarchical Organizations for Multi-core Architectures;Frontiers of High Performance Computing and Networking – ISPA 2006 Workshops;2006

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